Threshold voltage (Vt) increase in metal oxide semiconductor field effect transistors (MOSFETs) due to Bias Temperature Instability (BTI) is a significant reliability concern in high-K (high dielectric constant) metal gate complementary metal oxide semiconductor (CMOS) technologies. P-type metal oxide semiconductor devices (PMOS) are affected by Negative BTI (NBTI) and n-type metal oxide semiconductor devices (NMOS) are affected by Positive BTI (PBTI). FIG. 1 shows a p-type MOSFET 100 with a grounded gate and the left-hand drain-source terminal at voltage VDD, i.e., an NBTI stress condition. FIG. 2 shows an n-type MOSFET 200 with gate at voltage VDD and the left-hand drain-source terminal grounded, i.e., a PBTI stress condition. NBTI leads to PMOS Vt degradation and PBTI leads to NMOS Vt degradation.
Until recently, NBTI was considered to be more severe than the corresponding PBTI (PBTI has a negligible effect in NMOS with poly gates). However, with the use of metal-gates and high-K gate dielectrics, PBTI is becoming an equally important concern. With reference to FIG. 3, a typical ring oscillator structure (RO) 300 has been used as a popular NBTI monitoring circuit for its simplicity. Alternate stages experience different input voltage (either GND or Vstr) and hence NBTI and PBTI effects cannot be separated from RO output frequency degradation since RO frequency degradation after stress is due to both NBTI and PBTI. Such ring oscillator structures can be used when one BTI mechanism (PBTI or NBTI) is negligible compared to the other (NBTI or PBTI respectively) since the output frequency of the ring oscillator depends on both NBTI and PBTI degradation. The frequency of ring oscillator 300 is measured before stress. In stress mode, the ring is disabled from oscillation and the supply voltage and/or temperature are increased (e.g., Vdd raised to Vdd_stress) to facilitate an accelerated stressing of the devices. Since PBTI has been considered insignificant, the impact of stress on the NFETs 308 has been ignored. After suitably stressing the ring-oscillator circuit 300, its frequency is measured again (with Vdd back to normal), and the difference in the pre- and post-stress frequencies is a direct indication of the extent of NBTI related degradation of the PFET devices 306 in the circuit. Note that circles 306 indicate PMOS devices under stress while circle 308 indicates an NMOS device under stress. Note also that the connection between output 310 and input 312 is omitted for clarity, and that transistors are referred to herein generically as devices.
Co-assigned U.S. Pat. No. 7,642,864 of Chuang et al. discloses circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect. A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. One of more embodiments of the Chuang et al. invention advantageously separate out the NBTI and PBTI effects while maintaining simplicity of the circuit structure.
With reference to FIG. 4, in one or more embodiments of the invention of Chuang et al., PBTI and NBTI measurement systems are combined into a single ring-oscillator system 400 (which replaces an inverter), using a two-high stack for both PFET and NFET devices, with parallel PFET and NFET devices 410, 412 that ensure the application of appropriate stress voltages to the devices under test (DUTs) in stress mode. The repeating circuit structure 400 includes stacked PMOS device under test 402 and PMOS PB 404, as well as stacked NMOS NB 406 and NMOS device under test 408. N0 414 is the input and N1 416 is the output. The top and bottom rails are numbered, respectively, 418, 420. The extra devices used to provide isolation functionality are referred to as repeating-circuit-structure control circuitry, for example, devices 404, 406, 410, 412 (similar nomenclature is used for devices 504, 506, 510, 512 discussed below). The gates of all devices 404 may be interconnected to a p-stress enable terminal, the gates of all devices 406 may be interconnected to an n-stress enable terminal, the gates of all devices 410 may be connected to a p-parallel terminal, and the gates of all devices 412 may be connected to an n-parallel terminal.
In NBTI DC stress mode input 414 is grounded and the elevated stress voltage is applied to the top rail 418 and the gates of devices 404, 410, 412. Bottom rail 420 is also grounded (ground symbols in FIG. 4 represent this condition), as is the gate of device 406. This results in a ground appearing also on output 416, with devices 404, 406, 408, 410 off and device 402 stressed. The ground at 416 will also result in stressing the next PMOS device 402 in the next repeating structure 400.
In the device of FIG. 4, the gate voltage of PDUT 402 and NDUT 408 is in common, and the gate voltage of the DUTs is driven by the previous stage.
Further details re the PBTI stress mode and the measurement mode are provided in the aforesaid U.S. Pat. No. 7,642,864.